A Load-Balanced Switch with an Arbitrary Number of Linecards - Infocom '04

The load-balanced switch architecture is a promising way to scale router capacity. It requires no centralized scheduler, requires no memory operating faster than the line-rate, and can be built using a fixed, optical mesh. In a recent paper we explained how to prevent packet mis-sequencing and provide 100% throughput for all traffic patterns, and described the design of a 100Tb/s router using technology available within three years. But there is one major problem with the load-balanced switch that makes the basic mesh architecture impractical: Because the optical mesh must be uniform, the switch does not work when one or more linecards is missing or has failed. Instead we can use a passive optical switch architecture with MEMS switches that are reconfigured only when linecards are added and deleted, allowing the router to function when any subset of linecards is present and working. In this paper we derive an expression for the number of MEMS switches that are needed, and describe an algorithm to configure them. We prove that the algorithm will always find a correct configuration in polynomial time, and show examples of its running time. I. BACKGROUND Our goal is to identify router architectures with predictable throughput and scalable capacity. At the same time, we would like to identify architectures in which optical technology (for example optical switches and wavelength division multiplexing) can be used inside the router to increase capacity by reducing power consumption. In a previous paper [1] we explained how to build a 100Tb/s Internet router with a single-rack switch fabric built from essentially zero-power passive optics, but without sacrificing throughput guarantees. Compared to routers available today, this is approximately 40 times more switching capacity than can be put in a single rack, with throughput guarantees that no commercial router can match today. The key to the scalability is the use of the load-balanced switch, first described by C-S. Chang et al. in [2]. In [1] we extended the basic architecture so that it has provably 100% throughput for any traffic pattern, and doesn’t mis-sequence packets. It is scalable, has no central scheduler, is amenable to optics, and can simplify the switch fabric by replacing a frequently scheduled and reconfigured switch with a single, fixed, passive mesh of WDM channels. This work was funded in part by the DARPA/MARCO Center for Circuits, Systems and Software, by the DARPA/MARCO Interconnect Focus Center, Cisco Systems, Texas Instruments, Stanford Networking Research Center, Stanford Photonics Research Center, and a Wakerly Stanford Graduate Fellowship. 1